This invention relates to receiver equalizer circuitry, and more particularly to receiver equalizer circuitry having offset voltage compensation circuitry. The equalizer circuitry is intended for implementation on an integrated circuit (“IC”), especially an IC fabricated using, for example, 28 nm CMOS technology. The equalizer circuitry is further intended for use in receiving and equalizing (i.e., improving the quality of, and therefore the ability to recover data information from) a high-speed serial data signal. For example, the signal to be equalized may have a bit rate in the range of about 20-25 Gigabits-per-second (“Gbps”).